Abstract:

The performance of SoC is based on the efficiency of its bus. We propose a bus performance model which demonstrates the relations between the bus perf ormance and several substantial features of a SoC system. We also present carefully the analysis of the impact which is exerted on the bus performances   by the improvement of the pipeline stages of a bus. We design an efficient pipelined bus from the analysis results, and compare its efficiency with that  of the bus which performs the same transport protocols but do not support the pipeline, and mention one of its implementations on 32-bit SoC with milli  ons of gates.

Key words: （SoC, pipelined busl performance model）