| [1] |
QIN Wen-qiang, WU Zhong-cheng, ZHANG Jun, LI Fang, .
Design of convolutional neural network acceleration system based on heterogeneous platform
[J]. Computer Engineering & Science, 2024, 46(01): 12-20.
|
| [2] |
GUI Dan, YU Zong-jie.
An automatic calculation system of arbitrary waveform THD for small signal amplification circuit
[J]. Computer Engineering & Science, 2022, 44(07): 1199-1206.
|
| [3] |
CHEN Xiao-fan, YANG Zhi-jie, PENG Ling-hui, WANG Shi-ying, ZHOU Gan, LI Shi-ming, KANG Zi-yang, WANG Yao, SHI Wei, WANG Lei.
A verification framework of network on chip for neuromorphic processors
[J]. Computer Engineering & Science, 2022, 44(05): 769-778.
|
| [4] |
XIA Jun1,Qian Lei2,YAN Wei3,CHAI Zhilei1.
An FPGA-based HEVC post-processing
CNN hardware accelerator
[J]. Computer Engineering & Science, 2018, 40(12): 2126-2132.
|
| [5] |
GAO Ying1,ZHANG Zheng2,WANG Fenghua1,GUO Shuxia3.
Survey on complex electromagnetic
environment modeling and visualization
[J]. J4, 2014, 36(09): 1742-1749.
|
| [6] |
WANG Zhanling,ZHANG Dengfu,LI Yunjie.
Design of a detection system for 1553B
bus devices based on ARM and FPGA
[J]. J4, 2014, 36(06): 1005-1010.
|
| [7] |
ZHAO Guohong,HU Yongting,LI Tao,SUN Zhigang.
Design and implementation of output scheduling
IP core based on packet descriptor
[J]. J4, 2014, 36(03): 426-432.
|
| [8] |
XUE Xiao,LI Huiqin.
Design Approach to the Service Systems of Cluster Supply Chain
[J]. J4, 2010, 32(5): 161-164.
|
| [9] |
QIN Hui1,3,HU Jianpeng2,DING Zhigang1,3.
Design and Implementation of a ServiceAce IT Service Desk System
[J]. J4, 2010, 32(10): 161-164.
|
| [10] |
.
[J]. J4, 2007, 29(5): 54-55.
|
| [11] |
.
[J]. J4, 2007, 29(5): 37-40.
|
| [12] |
.
[J]. J4, 2006, 28(9): 129-131.
|
| [13] |
.
[J]. J4, 2006, 28(7): 7-10.
|