Abstract:

With the development of FPGA, more and more attention has been paid to FPGA based computing acceleration. And random number generators are frequently used in many of these applications. In this paper, a hardware structure for random number generation based on the Galois type the LFSR and Leap Forward method is proposed. By analyzing the characteristics of the proposed structure, some methods to improve the clock frequency and to save the hardware resources are put forward. A random number generator with 16bit outputs based on the above structure is implemented on the Xilinx Vertex 6 FPGA. This generator occupies only 6 slices, while the frequency and the throughput are as much as 951 MHz and 15.2 Gbps. The KS method is used to test the quality of the generated random numbers, and the CDF curve of the generated 105 random numbers is compared with the theoretical one.

Key words: linear feedback shifted registers;FPGA;random numbers