J4 ›› 2012, Vol. 34 ›› Issue (9): 197-200.
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Yankai,SHUANG Kai
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Abstract:
A digital signal processing system is usually implemented with Field Programmable Gate Arrays (FPGA) in order to be fast, low power, etc. The floatingpoint arithmetic must be translated to the fixedpoint arithmetic which is used on FPGA currently. The process of a floatfixed conversion is complex, the period is long and the precision is proved to be low. Using the merit of floatingpoint arithmetic which can offer high precision and wide dynamic range, the paper puts forward an improved fixed point and basic arithmetic rule, details how to realize the following basic modules: shift bits, addition/subtraction, multiplication and division. Finally, we take a digital filter, which is composed of basic modules, as an example. The simulation of the system shows that the improved fixed point format is higher in accuracy,wider in range than fixedpoint computing, and it can effectively avoid overflow.
Key words: arithmetic accuracy;basic arithmetic;FPGA
Yankai,SHUANG Kai. An Algorithm of Increasing FixedPoint Accuracy for Signal Processing Systems with FPGA[J]. J4, 2012, 34(9): 197-200.
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http://joces.nudt.edu.cn/EN/Y2012/V34/I9/197