Abstract:

Threedimensional Integration Circuit (3D IC) is a promising technology to mitigate the interconnect challenges in submicron integrated circuit chip design. 3D IC is a best choice for cache design dominated by lots of global interconnects. In addition to several 3D cache designs, we report a new architecture design methodology of cache using 3D IC, and propose a corresponding energy and delay model tool, 3D SCacti, to explore the cache design space. By searching the design space and minimizing the cost function, 3D SCacti can find the optimal result. By comparing its results with those obtained from a wellknown model, 3D Cacti, 3D SCacti can effectively enlarge the design space. Finally, the optimal results under different process generations are also analyzed.

Key words: 3D IC;Cache;simulator;architecture design