Abstract:

Router chip is a key component of interconnection network. A novel router microarchitecture is presented, which supports the fully adaptive Dimensional Bubble Routing Algorithm (DBRA). According to the characteristics of DBRA, the design of input buffer, arbiter and switch of router is optimized. The area and delay of router chip is evaluated by Design Compiler under the process of TSMC 40nm. The results show that the novel router chip is easier to achieve the higher frequency compared with the router chip based on Dauto’s methodology.

Key words: router chip;fully adaptive dimensional bubble routing algorithm;input buffer;arbiter and switching;Duato’s methodology