Abstract:

Head-of-line (HOL) blocking limits the throughput of high radix switches. An efficient architecture, OEASC, is proposed for highradix switches. This architecture takes advantages of two costeffective strategies for dealing with the HOL blocking problem. The first is referred to as asymmetric crossbar(ASC), through which a N×N switch can be formed by N/m smaller m×N asymmetric crossbars, and the second is oddeven queues scheme, through which the resources (mainly memory queues) of the switch can be used more efficiently. A tilebased microarchitecture of 32×32 high radix switch is proposed. Clock cycleaccurate simulation shows that the impact of HOL blocking is nearly all eliminated and the switch throughput can be as high as 98.6%. The proposed OE-ASC architecture shows up to 7.9% of throughput over ASC with buffer depth 16, and can achieve comparable performance with half buffers.

Key words: high radix router;interconnection network;throughput;headofline blocking