Abstract:

The Architecture Analysis and Design Language (AADL) is a popular language for embedded system development in industrial control, automotive, aerospace and other mission critical and realtime fields. In order to validate the schedulability of the established model at early stage, we propose a new method which can translate the AADL model into time automaton model. The scheduling strategy of the AADL model is mapped to the template of time automaton model, and we define the specific rules of translating the AADL execution model and behavior model. The generated model can be simulated and checked through the tool UPPAAL, to analyze the schedulability of the original model. Finally, the project describes the whole process of AADL modeling, model transformation and model verification, and proves the validation of the method.

Key words: architecture analysis and design language;time automata model;model transformation;UPPAAL;schedulability verification