• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2013, Vol. 35 ›› Issue (4): 24-28.

• 论文 • Previous Articles     Next Articles

Survey and design of chiperror
correcting algorithm in memory system  

LI Yongjin,MAO  Jianbiao,HUANG  Jinfeng   

  1. (School of Computer Science,National University of Defense Technology,Changsha 410073,China)
  • Received:2012-04-15 Revised:2012-08-21 Online:2013-04-25 Published:2013-04-25

Abstract:

Memory is an important part of computer systems, and it is selfevident that the accuracy of information access has meaningful effect upon the entire system. As computer applications are widely used, memory error detection and correction is an effective means to improve the reliability of storage system. The storage system can recover correct data through ECC (Error Correcting Code) when errors occur in memory. This paper introduced some ECC algorithms used in the current computer storage systems, and analyzed the limitations of these algorithms. To cover these shortages, we proposed a chiperror correcting code based on the Bossen’s 2redundant badjacent error coding, gave the process of coding and error correction coding of this algorithm, and then used the language of verilog HDL to do the logic design. The simulation results show that the algorithm can effectively correct all singlebyte errors, and can detect most of the multiplebyte errors.

Key words: memory;ECC;2redundant badjacent error;chiperror correction