Abstract:

In order to design a lowdelay and lowoverhead manycore NetworkonChip (NoC), the paper proposes an Architecture Utilizing 3D Stack Hierarchical Dualchannel NoC (AUSHDN) and KILL（Kill If Less Linear）rule is used to determine the number of processing cores in each group of AUSHDN. What's more, the prototype of the AUSHDN system is established based on the Graphite simulator from MIT. In AUSGHN system, 3D stack Hierarchical multilevel internetonchip is employed and different communication link is used to transfer control and data signal according to different content of communication. The results of simulation test in prototype system show that: compared with the traditional 2D NOC, the power consumption has reduced by 20% and the time delay has shortened by 30%. Meanwhile, the hierarchy feature of the AUSGHN system guarantees its good scalability.

Key words: 3D stack;manycore prototype;lowpower;lowdelay;dualchannel