Abstract:

Evaluating the memory access latency has important significance for optimizing application patterns and data placement. However, cache, multithreading, data prefetching and other techniques have serious interference with the accuracy of measurement of memory access latency. A measurement model based on variable strides is designed and implemented. According to userspecified strides, we create a sequence ring in a space, and circularly access this ring to obtain the average time as the memory access latency.  Finally, we measure an Intel common processor and FT processor’s memory latency by different data size, stride and thread, and make the data contrast with each other. This model can display the memory hierarchy and display memory latency precisely.

Key words: Memory latency;variable stride;measurement;SMT;multicore processor;FT Processor