Abstract:

We propose an implementation scheme for a TYPE-I M-LVDS receiver based on TIA/EIA-899 standard.A novel common-mode voltage shift circuit is designed to realize an input common-mode range that is beyond the rail of the power voltage,which can simplify the post stage circuit,thus saving area and power consumption.The pre-amplifier in the receiver can provide a fixed magnification for input signals,and the hysteresis comparator brings hysteresis effect to the system.The chip is fabricated in GSMC 0.18 μm 1P6M CMOS technology,and the test results indicate that the receiver has an input commonmod range of -1.4 V~3.8 V,a signaling rate greater than 250 Mbps,and a typical hysteresis voltage is 28 mV.

Key words: M-LVDS;high-speed interface;common-mode voltage;hysteresis