Abstract:

To reduce the overall power consumption of high performance ICs, we compare the high threshold voltage technology with the low one and analyze their different applications. In order to reduce the total power consumption, we use the low threshold voltage technology to reduce the dynamic power consumption. Firstly, we analyze internal power consumption, timing and size of standard cells in the 40nm technology. Under the same delays we then compare the power consumption of the two kinds of inverter chains composed by standard cells with the two thresholds, respectively. We also analyze the dynamic power consumption of the benchmark and AES circuits which are synthesized by high threshold voltage and low threshold voltage  respectively. By comparison, we find out the corresponding threshold voltage design approach for lower power design under the same clock cycle. The synthesis results show that for the circuits with a large ratio of dynamic power consumption to the total power consumption , low threshold voltage design can reduce power consumption; while the ratio of dynamic power consumption is not large, if the low threshold synthesis slack  is positive or the high threshold synthesis slack is negative and the low threshold synthesis slack is zero, a low threshold voltage design can reduce power consumption; or when both of their synthesis slacks are zero, a  high threshold voltage design can achieve lower power consumption.

Key words: threshold voltage;standard cell;dynamic power consumption;DC synthesis