Abstract:

Register files in superscalar processors usually adopt the multiport structure to support the wide issue, however, this structure brings in problems such as prolonging access speed, increasing in silicon areas and higher power consumption.We design a 64*64 bit multiport register file which can concurrently accomplish 8 read operations and 4 write operations in one single clock cycle.We improve the conventional singleended memory cell structure and purpose a new structure, which combines the powergating and the bitline floating techniques, and the transmission gate is used in all ports to accelerate the access speed.Simulations are conducted on Hspice with PTM 90 nm, 65 nm, 45 nm and 32 nm technology models compared with the conventional singleended structure, the proposed method  can significantly improve the performance of register files, the delay of write logic 1 decreases more than 32%, and the total power consumption decreases more than 45%; the stability of memory cells is also improved.

Key words: register file;single-ended;power-gating;bit-line floating