Abstract:

Since the existing hardware architecture for Hash algorithms can only implement a few algorithms, we design a reconfigurable IP, which can implement seven Hash algorithms including SM3, MD5, SHA1 and SHA2 family, and it can meet the demand of a system for algorithm diversity. By analyzing all these Hash algorithms and estimating their similarity, the design reuses adders and registers to the maximum extent and therefore greatly reduces the total area. Besides, the design is flexibly configurable and can access the memory directly. The implementation results based on the FPGA of Stratix II of Altera Corporation show that, in comparison with the existing designs, the maximum frequency can achieve 100MHz, the whole area is decreased by more than 26.7% and the throughputperarea for each of the seven algorithms is increased.

Key words: Hash algorithm;SM3;MD5;SHA;basic arithmetic unit;reconfigurable;high performance