Abstract:

We propose a calibration technique based on binary capacitor DAC. We also design a lowpower highprecision dynamic comparator using 65nm CMOS technology. Simulation results based on layout show that our proposal can reduce the offset less than 0.25mV under 1.2V supply. It achieves 0.33μW power dissipation, an increase of 57% in comparison with the comparators without calibration.

Key words: offset voltage;mismatch;dynamic comparator;calibration