Abstract:

Traditional stimulus generation mechanism is laborintensive and hard to reuse in the design process of systemonachip (SoC), thus the simulation efficiency is affected seriously. To solve this problem, we construct a virtual SoC verification platform based on the reusable stimulus generation mechanism. The verification platform calls a port stimulus file through a reusable stimulus generation module, and the stimulus file is converted into the timing signals that correspond to the ports of the verification circuit. The function verification of universal synchronous/asynchronous receiver/transmitter, interrupt and timer demonstrates the observability, controllability and feasibility of the stimulus generation mechanism. The verification result analysis shows that it only needs to modify the firmware and port stimulus files when different function points are to be verified. As a result, the amount of code changes during the reuse of the verification platform is reduced, the flexibility and efficiency are improved, and the SoC verification time is shortened.

Key words: reusability;stimulus generation mechanism;virtual SoC verification platform;port stimulus file