Abstract:

3D microprocessors have advantages of high-level integration, short global interconnection and more connecting parts. However the traditional 3D topology cannot take full advantage of the characteristics of 3D integrated circuits in the vertical direction. It is difficult for these structures to meet the requirements of large-scale many-core processors, such as short diameter, high-bandwidth and highly scalability. We propose a 3D on-chip interconnection network topology, called V-Spidergon. In the horizontal layer, the V-Spidergon adopts the Spidergon topology in the horizontal layer and a domain-based interconnected structure in the vertically direction. The entire vertical network is divided into multi-level domains according to the hierarchical domain thought, and every domain interconnects with each other. Simulation results show that the time delays in 8 layers, 16 layers and 32 layers of the V-Spidergon are lower than those of the 3D-Mesh by 15.1%, 28.5%, 55.7% respectively, and are also lower than those of the NoC-Bus by 11.5% 32.7% and 77.6% respectively; under injections of 15% and 100% load rates, the average time delay of the V-Spidergon does not increase with the growth of horizontal layers.

Key words: many-core microprocessor, network on chip, 3D integrated circuit, 3D-Mesh, NoC-Bus, hierarchical vertical domain