Abstract:

With the continuous development of semiconductor technology, 3D chip technology has become a hot research highlight, and the process of chip testing has a new requirement for “mid-bond tests”. But for the “mid-bond test”, “one testing after every bonding” makes some dies repeat testing, thus resulting in an increase of test time. We put forward a "one testing after multiple bondings" testing process which considers the effect of test power consumption and "theoretical manufacturing cost". Besides, we also introduce a breadth first traversal algorithm, which combines the relevant parameters of ITC'02 circuit. The combination reflects our proposal's practical significance in actual production.

Key words: mid-bond test, one testing after multiple bondings, power constrains, theoretical manufacturing cost constrains