Abstract:

With the advance of network information age, various electronic products emerge, making people’s life much intelligent and convenient. However, the great convenience also introduce major potential safety hazard. Crypto chips are one of the important means to guarantee information safety, so it is urgent to promote their safety. Taking the glitch attacks on the block cipher chip S-box proposed by Stefan et al as the model background, based on FPGA, we put forward a glitch attack resistance scheme for block cipher chip S-box by adding synchronization registers. The properties of CMOS devices and the Signal Tap function embedded in the QuatusⅡ software of Altera company demonstrate from the perspectives of theory and simulation that the proposed scheme can remarkably reduce the number of glitches, lower the glitch correlation of circuits of all levels , decrease success rate of attacks, improve the security of block cipher S-box and provide subsequent security protection for FPGA crypto chips.

Key words: block cipher, S-box, glitch attacks, FPGA, synchronization register