With the continuous progress of microelectronic technology, the static random access memory （SRAM） occupies the majority area of modern systemsonachip (SoC), so the defect rate of the SRAM has become an important factor affecting the yield of chips. We propose a scalable memorybuiltinselfrepair algorithm（SMBISR）based on error checking and correcting (ECC) check code. With the same redundant SRAM structure, the correcting capability of the ECC code can enhance the faulttolerant capability, thus increasing the rate of finished product of chips effectively without increasing test time. We implement the algorithm on the RTL, and the evaluation of the backend design shows that its working frequency can reach 1GHz while the area overhead is only 1.5%.