Abstract:

Energyefficiency becomes one of the key constraints in the current design of processors. Since the instruction unit accounts for considerable chip area and power consumption, we propose an L0 instruction cache (L0 IC) to alleviate the power cost of the instruction units. The L0 IC has small size so the access power is relatively small. Meanwhile the L0 IC is tightly coupled with the pipeline in order to clockgate part of the pipeline logic when instruction fetches hit in the L0 IC. The recent studies on the L0 IC are reviewed. The development and application of each L0 IC design is presented. Meanwhile, future work on the L0 IC design is discussed.

Key words: high energyefficiency, L0 cache, instruction cache, microarchitecture design