Abstract:

Tag access and comparison consumes a significant portion of instruction cache’s energy. We propose a power-efficient instruction cache based on inference: asymmetric instruction cache. Sequential instructions and non-sequential instructions are treated differently and asymmetric ID invalid bits are applied according to lower ration feature of non-sequential instructions. Hit inference technique is used to reduce the number of tag comparison in cache. And adaptive-length instruction fetch techniques are designed to reduce the miss rate of sequential instruction blocks. Compared with tagless hit instruction cache (TH IC), both energy efficiency and performance of the proposed method are improved. Experimental results show that the overall energy consumption is reduced by 40%～60% over L1 Cache for most of the selected SPEC2006 benchmarks. Energy-delay2 product (ED2P) of instruction fetch is 50% lower than that of L1 cache and 17% lower than that of TH IC.  

Key words: energy consumptions, instruction cache, energy-delay2 product, hit inference