3D-SIC, which improves the system integration and overall performance validly by using the TSV technology, makes vertical interconnect circuits come true. Since the number limitation of TSVs and pins for testing and test power consumption all have  effects on 3D-SIC test time, we propose a testing scheme based on the concept of container-packing problems, which can optimize the test scheduling for the “single tower” structure which only has one chip in each layer and the “multiple towers” structure which has more chips in each layer. This optimization scheme can not only control the numbers of test pins and TSVs for testing and the power consumption but also reduce test time effectively. Experimental results show that the proposed scheme has obvious optimization results: the “single tower” structure can reduce up to 45.28% of the testing time while the “multiple towers” structure can reduce up to 27.78%.