Abstract:

Manycore processor design faces a great challenge in terms of chip area utilization. How to improve the proportion of the computing units in the limited chip area is a hot topic in the research on manycore architecture. We focus on the design of the instruction cache on the manycore processor. The instruction cache is shared among several processing cores in order to improve the pipeline performance. We propose a design of shared instruction cache and implement cycleaccurate performance simulation on it. The RTL codes of the shared instruction cache are synthesized to get the area cost and timing results. Experimental results demonstrate that the shared instruction cache can decrease 11% to 27% miss rate and improve the pipeline performance by 4% to 7%.

Key words: many-core processor, instruction cache, architecture optimization