As the complexity of integrated circuit design increases exponentially, functional verification has become a bottleneck in large-scale chip design. And in multi-core processor design, Cache coherency protocols are very complex and difficult to verify. We propose a random test generation method based on Bayesian network for simulation-based verification to solve the state space explosion problem of Cache coherency protocols. We discuss the Cache coherency protocol, analyze the coverage directed test generation (CDG) method based on Bayesian network reasoning, and apply the method to Cache consistency verification. Taking the verification of the Cache coherence protocol of the FT processor as an example, the results show that the CDG method can increase coverage by nearly 30% in comparison with the pseudo-random test.