• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

Computer Engineering & Science

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Fast hardware implementation of on-chip
Nor Flash wear leveling based on heap-sort
 

XU Shu-tao1,HUANG Kai1,HUANG Kai-jie2,JIANG Xiao-wen1,ZHANG Xiao-meng1   

  1. (1.College of Information Science & Electronic Engineering,Zhejiang University,Hangzhou 310027;
    2.Sec-Chip Co.,Ltd.,Hangzhou 310012,China)
  • Received:2016-05-18 Revised:2016-10-17 Online:2017-11-25 Published:2017-11-25

Abstract:

Traditional implementation methods of Flash wear leveling mainly base on file system and focus on Nand Flash, while the wear leveling of Nor Flash is ignored. Nor Flash sometimes fails to be embedded in the operating system, and the cost can be too huge, so wear leveling cannot be implemented through the file system. We implement Flash wear leveling on hardware to solve this problem and reduce software cost. Four modules, which are wear leveling, address mapping, garbage collection and Flash interface unit, are implemented by Verilog. When a write request arrives, the sector which has the minimum erase time is found by the heap-sort, the virtual address is connected to the sector's physical address, and the address mapping list is updated. When the number of garbage sectors reaches a threshold value, garbage collection starts. Finally,  experimental results show that the operation time of initialization, heap deletion and read in hardware wear leveling algorithm is at most 14, 16.4 and 17.8 times faster than those of software algorithms respectively.

Key words: Nor Flash, wear leveling, hardware implementation, heap-sort, Verilog