With the development of the system on chip (SoC) technology, the communication among chip modules is frequent. Asynchronous systems are popular due to low power consumption, speed up potential and strong anti-jamming capability, however, the design is complex and the problem of cross-clock-domain data transmission needs to solve. At present the most popular way is the first input first output (FIFO). As the complexity of the SoC increases, there are hundreds of modules. So a system integration using the FIFO consumes disproportionate  resources and power. Through the analysis of the characteristics of asynchronous transmission, we propose a way to use indicator signals to achieve cross-clock-domain data transmission. Compared with the FIFO, the proposal can reduce power consumption and its design complexity without performance decrease. Simulations on the two chip modules (CPU and FPGA) using Verilogon and the Vivado hardware of Xilinx company verify its feasibility. Compared with the design of the FIFO method, the proposed method has better application value.