As a key component of All-Digital Phase-Locked Loop (ADPLL), Digitally Controlled Oscillator (DCO) provides a high-frequency output clock. The DCO performance directly affects the frequency range and jitter performance of ADPLL. This paper proposes a DCO based on all-digital standard cell library design. The structure includes the coarse, medium and fine adjustment stages, which achieves a high frequency range of 0.5 GHz~2.6 GHz and a high adjustment resolution of 0.8 ps. The DCO is designed and implemented in an advanced process. Based on this DCO, an ADPLL is designed and implemented. The system jitter is less than 2 ps and the power is 10 mW.