Instruction stream delivery and instruction Cache failure are two of the important reasons for processor energy dissipation. Programs based on loosely coupled RISC instruction sets exacerbate such energy consumption. Cachelimited network devices such as routers and switches suffer more performance degradation and power consumption due to instruction related processing. This paper focuses on network packet forwarding, which is one of the most important network functions. Thought analyzing instruction characteristics of network packet forwarding, we redefine the RV32 compressed instruction extension set based on the RISC- instruction set architecture and test it by Spike simulator. Experimental results show that the optimized compression rate is reduced to 70% and the dynamic instruction compression rate is 90%. Meanwhile, under the same Cache conditions, our RV32C set can reduce the instruction Cache failure by 30%~70% in comparison to the standard RISC- set.