Phase Locked Loop (PLL) is an essential part of high-performance SOCs that provide the chip with a system clock. This paper presents a novel All-Digital PhaseLocked Loop (ADPLL) structure for high-performance SOC applications and a novel high-resolution Time-to-Digital Converter (TDC)  improves the phase detection precision and reduces the TDC phase noise and improves the PLL jitter performance. In the nanometer process, the ADPLL system is implemented by using digital standard cells, which solves the bottleneck problems such as poor portability to new process, big area of passive devices, and poor antinoise ability in analog circuits. The system has the maximum frequency of 2.6GHz and the jitter performance less than 2 picoseconds.