Because of their high computational performance and energy efficiency ratio, arraybased manycore processors have been widely used in the high performance computing field. To build the future high performance computing systems, processors must solve the severe challenge of ‘memory wall’ and the core synergy problem. The kernel of the common arraybased manycore processor uses a singlethreaded structure to reduce the overhead, but the memory access demand is higher. In this paper, the hardware simultaneous multithreading technology is introduced into the single core structure. Aiming at the problem that the hit rate of the L1 instruction Cache is significantly reduced with the increase of the number of threads, this paper proposes an instruction Cache structure (Redundancy Instruction Cache) for the arraybased manycore processors. Based on this structure, a FIFO replacement strategy and an analogous LRU replacement strategy are proposed. Experimental results demonstrate that, based on the optimized Cache structure design, the instruction Cache miss rate of the dualthreaded structure is decreased by 25.2% and the CPI performance is increased by 30.2%.