The protocol type and level of traditional packet parser are fixed, which lacks support for the new network protocols, and restricts the programmability of network devices. We abstract the formalization of the parsing process and implement a protocolindependent programmable parser based on the FPGA. The support for the new protocol does not require hardware changes, except remapping the parsing graph. Based on this mechanism, a series of optimization techniques are introduced to overcome the inherent serialization of packet parsing, save storage resources, and provide an effective solution to the realization of high speed programmable message parsing. We evaluate hardware cost and performance on the platform of generalpurpose multicore and high performance FPGA. Experimental results show that the programmable parser can greatly improve the performance of message parsing, quickly analyze general network protocols and potential network protocols, and effectively support the rapid development of customized network protocols.