Because of its high computational performance and energy efficiency ratio, array-based many-core processors have been widely used in the high performance computing field. To build future high performance computing systems, processor must solve the severe challenge of ‘memory wall’ and core synergy problem. In a typical array-based many-core processor, the core adopts the single-threaded structure to reduce overhead. However, the demand for memory access is higher. We introduce the hardware simultaneous multithreading technology into the single core structure. Aiming at the problem that the utilization rate of the singlecore multithreaded L2 cache is significantly low, we present a L2 cache partitioning mechanism (thread-based cache partitioning) for the array-based manycore processor. Experimental results demonstrate that, based on the L2 cache partition mechanism, the miss rate of the L2 instruction cache is decreased by 18.59%, the miss rate of the L2 data cache is decreased by 6.60% and the CPI performance is increased by 10.1%.