Due to everincreasing demand for memory bandwidth, memory access rate and interconnect density become higher and higher. DDR4, as a very popular and fast parallel interconnect technology in main memory, features 100ps level of signal rise/fall time, which brings noticeable crosstalk issue between signals. Thus we design a trilinear disturbance model based on a certain DDR driver model and its board-level embedded application, and respectively simulate the effect of four factors on striline transmission crosstalk from the time domain angle, including line space, disturbing source phase, date rate, and coupling transmission line length. The results show that the crosstalk is close to 0 mV when the line pace reaches 5 times of dielectric thickness and different disturbing source phases cause double two-dimensional difference in total crosstalk. For a certain data rate, a periodic relationship between coupling transmission line length and extreme value of crosstalk is revealed. Utilizing this relationship to design reasonable line length for DDR data groups, crosstalk maximum value is avoidable.

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