Reconfigurable array processor has the characteristics of large amounts of memory data, high data parallelism, less global data reuse and obvious data locality. Aiming at these characteristics, this paper proposes an intra-cluster local-priority efficient-access switch in distributed Cache. The switch can make 4×4 PEs to access 4×4 Caches in parallel. Xilinx’s ZYNQ series chip XC7Z045 FFG900-2 FPGA are used for FPGA synthesis. The switch can support the concurrent read and write operations of 16 intra-cluster PEs in the absence of conflicts, the working frequency can reach 221 MHz, and the memory bandwidth can attain 7.6 GB/s. The image texture extraction algorithm based on Gray-level Co-occurrence Matrix (GLCM) is implemented on this switch. The data memory bandwidth reaches 478.125 MB/s, and the execution time is 0.24ms.