Abstract: General-Purpose Graphics Processing Units (GPGPUs) his been widely used in modern high performance computing systems. The Single-Instruction Multi-Thread (SIMT) execution model of GPGPUs results in a lower page hit rate, and requires Page Walk Cache (PWC) to reduce the actual number of page table accesses for irregular applications. There is a lot of redundant information in the traditional PWC and the capacity is limited, so the actual effect is not good. We analyze the information redundancy in the traditional PWC and propose a new structure: Compressed PWC. Compressed PWC completely eliminates redundant information and compresses the space while keeping the same search overhead unchanged, so that PWC can record more page table access history, thereby effectively reducing the number of page table accesses during the address translation. Experimental results indicate that, compared with the traditional PWC of the same capacity, compressed PWC can significantly improve the efficiency of virtual-to-physical address translation.

Key words: general-purpose graphics processing unit (GPGPU), virtual-to-physical address translation, page walk cache (PWC)