Abstract: To meet the requirements of mapping multiple input data to multiple output channels in ASIC (application specific integrated circuit) design, this paper proposes a data queue scheduling method that supports multi priority and multi output channels. Firstly, the proposed method can be used in a wide range of applications, either to achieve load balancing by scheduling in a random mode or to diffe- rentiate the quality of service (QoS) by configuring different priorities. In the random mode, multiple output channels in idle state will receive input data in round-robin fashion. In the QoS mode, all input sources and output channels are divided into different priorities, so that a certain output channel only receives data from input sources with the corresponding priority. Secondly, this method has the advantage of low hardware implementation cost, due to multiple output channels sharing a single arbiter instead of multiple individual arbiters. The proposed method is applied in the network interface chip design of Tianhe supercomputer system to optimize the data queue scheduling for the software/hardware interface. The design is tested in the verification environment. Current test results show that, compared with the traditional single-output queue scheduler, the proposed method only increases the scheduling time cost by 3‰ to 2% and the hardware resource cost by about 1.5%, but achieves a two-fold increase in the speed of processing for direct memory read transactions. At the same time, when it is configured for QoS mode, the execution time ratio between high-priority threads and low-priority threads is about 1∶3, and it is also flexible for reconfiguration.

Key words: queue scheduling, priority, quality of service (QoS), arbiter