[1] |
WU Tie-bin, GUO Feng, WANG Di.
A survey of core computing architecture of high performance processors for exascale computing
[J]. Computer Engineering & Science, 2023, 45(05): 761-771.
|
[2] |
WANG Yu-lei, XIE Kai-liang, CHEN Si-yun, HU Jie, CHANG Sheng.
A universal design on hardware acceleration of convolutional neural networks
[J]. Computer Engineering & Science, 2023, 45(04): 577-581.
|
[3] |
LU Song, JIANG Ju-ping, REN Hui-feng.
Quick customization for RISC-V processor based on FPGA
[J]. Computer Engineering & Science, 2022, 44(10): 1747-1752.
|
[4] |
CHEN Feng-xian.
Cluster job runtime prediction based on NR-Transformer
[J]. Computer Engineering & Science, 2022, 44(07): 1181-1190.
|
[5] |
CHEN Xiao-fan, YANG Zhi-jie, PENG Ling-hui, WANG Shi-ying, ZHOU Gan, LI Shi-ming, KANG Zi-yang, WANG Yao, SHI Wei, WANG Lei.
A verification framework of network on chip for neuromorphic processors
[J]. Computer Engineering & Science, 2022, 44(05): 769-778.
|
[6] |
LI Tie-jun, MA Ke-fan, ZHANG Jian-min.
A parallel FPGA SAT solver based on incomplete algorithm
[J]. Computer Engineering & Science, 2021, 43(12): 2126-2130.
|
[7] |
BAI Yu-long, PAN Xing-yu, DUAN Ji-kai, YANG Yang.
A four-wing memristive chaotic system based on hyperbolic sine function and its FPGA implementation
[J]. Computer Engineering & Science, 2021, 43(10): 1744-1749.
|
[8] |
ZHAO Xiao-qiang, JIANG Jing-fei, XU Jin-wei, DOU Yong.
A dynamic remainder processing mapping model for convolutional neural network accelerator on FPGA
[J]. Computer Engineering & Science, 2021, 43(09): 1521-1528.
|
[9] |
LUAN Yi, LIU Chang-hua.
A deep neural network edge computing platform based on TPU+FPGA
[J]. Computer Engineering & Science, 2021, 43(06): 976-983.
|
[10] |
WANG Xia, ZHENG Long-fei, WANG Meng-jun, ZHANG Hong-li, WU Jian-fei, .
A radiation emission suppression method of high-performance FPGA
[J]. Computer Engineering & Science, 2021, 43(05): 814-819.
|
[11] |
GUO Hui, HUANG Li-bo, ZHENG Zhong, SUI Bing-cai, WANG Yong-wen.
Proto-Perf:Fast and accurate processor prototype performance evaluation
[J]. Computer Engineering & Science, 2021, 43(04): 579-585.
|
[12] |
SUN Zhao-peng, ZHOU Kuan-jiu.
A high performance FPGA-GPU-CPU heterogeneous programming architecture based on PCIe
[J]. Computer Engineering & Science, 2021, 43(04): 641-651.
|
[13] |
WU Jun-nan, OU Yang, LI Yan.
Design and implementation of a high performance computing user organization management system based on LAMP#br#
#br#
[J]. Computer Engineering & Science, 2021, 43(02): 235-241.
|
[14] |
LIU Jie, GONG Chun-ye, YANG Bo, GUO Xiao-wei, GAN Xin-biao, LI Sheng-guo, LI Chao, CHEN Xu-guang, XIAO Tiao-jie, MU Li-an, SONG Min, ZHAO Dong-yong, JU Yu-zhong.
YH-ACT:Parallel analysis code of thermohydraulics
[J]. Computer Engineering & Science, 2021, 43(01): 58-69.
|
[15] |
HAN Zhe, JIANG Jingfei, QIAO Linbo, DOU Yong, XU Jinwei, KAN Zhigang.
Design and implementation of event extraction model and accelerator based on FPGA
[J]. Computer Engineering & Science, 2020, 42(11): 1941-1948.
|