• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

Computer Engineering & Science ›› 2020, Vol. 42 ›› Issue (11): 1941-1948.

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Design and implementation of event extraction model and accelerator based  on FPGA

HAN Zhe,JIANG Jingfei,QIAO Linbo,DOU Yong,XU Jinwei,KAN Zhigang   

  1. (School of Computer,National University of Defense Technology,Changsha 410073,China)
  • Received:2020-06-11 Revised:2020-07-15 Accepted:2020-11-25 Online:2020-11-25 Published:2020-11-30

Abstract: Event extraction technology is important to achieve the quickly extraction of specific information, and it can be widely used in information retrieval, sentiment analysis and other scenarios. Chinese event extraction is more difficult than English event extraction due to the characteristics of Chinese language. Based on the stateoftheart English event extraction neural network model, a CEEDGCNN (Chinese Event Extraction based on multilayer Dilate Gated Convolutional Neural Network) is proposed, which is suitable for hardware implementation. CEEDGCNN achieves 71.71% F1score of trigger classification on the ACE2005 Chinese corpus. The accelerator of CEEDGCNN is designed and implemented, and the model size is further optimized by quantization. The accelerator can achieve 97 GOP/s on the Xilinx XCKU115 FPGA, which is 67 times faster than CPU.

Key words: FPGA, event extraction, dilate gated convolutional neural network, accelerator