[1] |
CHEN Jie, LI Cheng, LIU Zhong.
Convolutional neural network inference and training vectorization method for multicore vector accelerators
[J]. Computer Engineering & Science, 2024, 46(04): 580-589.
|
[2] |
MA Ke-fan, LI Bao-feng, ZHOU Yue-jin, WU Yuan-yuan, YU Yong-lan, DUO Rui-hua.
Design and implementation of a baseboard management controller on ZYNQ chip
[J]. Computer Engineering & Science, 2024, 46(02): 217-223.
|
[3] |
ZHAO Zhi-qiao, ZHOU Li, XUN Chang-qing, PAN Guo-teng, TIE Jun-bo, WANG Wei-zheng.
Efficient analysis of coherent hub interface protocol mixturing hardware and software
[J]. Computer Engineering & Science, 2024, 46(02): 224-231.
|
[4] |
QIN Wen-qiang, WU Zhong-cheng, ZHANG Jun, LI Fang, .
Design of convolutional neural network acceleration system based on heterogeneous platform
[J]. Computer Engineering & Science, 2024, 46(01): 12-20.
|
[5] |
ZHOU Li, ZHAO Zhi-qiao, PAN Guo-teng, TIE Jun-bo, ZHAO Wang.
RISC-V based design of graph convolutional neural network accelerator
[J]. Computer Engineering & Science, 2023, 45(12): 2113-2120.
|
[6] |
HU Qing-meng, , WANG Hong-bin, WANG Jun-zhong.
A Chinese event detection method based on nugget proposal network with part-of-speech attention mechanism
[J]. Computer Engineering & Science, 2023, 45(08): 1490-1497.
|
[7] |
YI Xiao, MA Sheng, XIAO Nong.
Running optimization of deep learning accelerators under different pruning strategies
[J]. Computer Engineering & Science, 2023, 45(07): 1141-1148.
|
[8] |
LIU Xiao-hang, JIANG Jing-fei, XU Jin-wei.
A fused-layer attention model accelerator based on systolic array
[J]. Computer Engineering & Science, 2023, 45(05): 802-809.
|
[9] |
WANG Yu-lei, XIE Kai-liang, CHEN Si-yun, HU Jie, CHANG Sheng.
A universal design on hardware acceleration of convolutional neural networks
[J]. Computer Engineering & Science, 2023, 45(04): 577-581.
|
[10] |
DU Jie, LUO Li-ming, SUN Zhong.
Event extraction technology based on ALBERT pre-trained model
[J]. Computer Engineering & Science, 2023, 45(04): 711-717.
|
[11] |
YANG Hao, ZHAO Gang, WANG Xing-fen.
A hybrid model for event trigger word extraction
[J]. Computer Engineering & Science, 2023, 45(01): 171-180.
|
[12] |
LU Song, JIANG Ju-ping, REN Hui-feng.
Quick customization for RISC-V processor based on FPGA
[J]. Computer Engineering & Science, 2022, 44(10): 1747-1752.
|
[13] |
CHEN Xiao-fan, YANG Zhi-jie, PENG Ling-hui, WANG Shi-ying, ZHOU Gan, LI Shi-ming, KANG Zi-yang, WANG Yao, SHI Wei, WANG Lei.
A verification framework of network on chip for neuromorphic processors
[J]. Computer Engineering & Science, 2022, 44(05): 769-778.
|
[14] |
LI Tie-jun, MA Ke-fan, ZHANG Jian-min.
A parallel FPGA SAT solver based on incomplete algorithm
[J]. Computer Engineering & Science, 2021, 43(12): 2126-2130.
|
[15] |
BAI Yu-long, PAN Xing-yu, DUAN Ji-kai, YANG Yang.
A four-wing memristive chaotic system based on hyperbolic sine function and its FPGA implementation
[J]. Computer Engineering & Science, 2021, 43(10): 1744-1749.
|