Abstract: Aiming at the linear bottleneck structure of MobileNetV2, we study the design scheme of the dedicated processor chip. Based on the Layer Fusion mode and the configurable block structure, we design a pipeline structure for bottleneck convolution as well as a corresponding analysis framework. Then, a design space is proposed accordingly, and a software simulator is used to traverse and compare the performance of various schemes in this space. We then find the rules for optimal parameter selection. The validity of the conclusion is verified by hardware behavior simulation. The study can help system chip designers to select or design a suitable MobileNetV2 processor IP design scheme based on their own resource constraints and performance requirements. The paper also provides some inspiration for future automatic processor design.

Key words: digital integrated circuit, convolutional neural network, accelerator, design methodology