Abstract: Object detection tasks usually use the non-maximum suppression algorithm (NMS) to remove redundant candidate boxes of convolutional neural network's outputs. Soft-NMS uses the method of gradually attenuating the score of candidate box to replace the method of directly deleting the candidate box larger than the predefined threshold in Hard-NMS, which can avoid deleting the overlapping object in the picture by mistake and improve the accuracy of the object detection task. However, the frequent change of candidate box score makes Soft-NMS more complex than Hard-NMS. In order to achieve high accurate, low-delay and low-power candidate box redundancy removals, this paper proposes a Soft-NMS based architecture, which uses logarithmic functions to optimize complex floating-point calculations and a two-level optimization structure with fine-grained flow and coarse-grained parallelism to improve the throughput of the algorithm. Experiments on Xilinx KU-115 FPGA show that our power consumption is 6.107 W, and the delay of processing 1000 boxes is 168.95μs. Compared with the Soft-NMS implemented by the CPU, the architecture achieves 36 times performance improvement and the performance power consumption ratio is 264 times that of CPU implementation. 

Key words: reconfigurable computing, object detection, non-maximum suppression