Abstract: MobileNet network is a deep neural network mode widely used in the embedded field. In order to solve the problem of low hardware implementation efficiency and achieve certain scalability under different hardware resources, a MobileNet network accelerator structure based on FPGA is proposed. According to the stacking structure characteristics of the network, a three-level pipeline acceleration array is designed, and the computing efficiency is over 70% within 4000 multipliers. A 150 MHz fully working demo on XILINX Zynq-7000 ZC706  development board achieves 156 Gop/s performance and 61% calculation efficiency, which is higher than other MobileNet network accelerators.

Key words: MobileNet network, convolutional neural network, hardware accelerator