Abstract: With the application of domestically developed Feiteng series high-performance DSP processors in the field of image processing, there is a strong demand for high-performance image processing algorithms on this platform. As the basic algorithm of image processing, Gaussian filtering can effectively filter out Gaussian noise in images, and it has been widely used in the field of image processing. According to the architectural characteristics of FeiTeng high-performance DSP and the characteristics of Gaussian filtering algorithm, the optimization of Gaussian filtering algorithm on Feiteng high performance DSP is realized. Optimization methods such as manual vectorization, control flow elimination, and loop unrolling are adopted to take full advantage of data-level and instruction-level parallelism, thereby reducing the number of data accesses and improving instruction efficiency. According to the DMA hardware and vector memory structure characteristics in the FT-MT2 core, optimizations such as ping-pong cache and DMA array transposition are performed to reduce the data transmission time and improve the data locality. Test results under various filter kernel sizes and image matrix scales show that, compared to the serial implementation of the Gaussian filter algorithm, the parallel optimization implementation achieves a speedup of 1.3~1.41. With cache enabled, compared with the running performance of the Gaussian filtering algorithm in the dsplib library on the TMS320C6678 platform, the acceleration effect is 1.15~1.71 times.

Key words: high performance DSP, Gaussian filtering, vector parallel optimization, DMA transmission optimization