Abstract: Issue queue is the out-of-order control unit of superscalar processors, and it is also a key component in the processors, which plays a decisive role in the performance of the entire processors. The paper proposes a dual-port issue queue structure that can effectively improve the performance of out-of-order superscalar processors. The queue can estimate the issue time of the instructions according to the correlation between the instructions, and allocate the instructions to different queues. The impact of two different launch strategies on performance is compared, and the strategy of marking the execution pipeline at the input end can obtain higher IPC performance, which can reach 10.68% at the maximum. At the same time, when the same launch strategy is adopted, the impact of the number of launch queue entries on performance is compared. Compared with 24 launch queues, 32 launch queues can improve the IPC performance by 2% on average, and 8.59% at most.

Key words: micro processor, out-of-order superscalar, issue queue