Abstract: In high-performance processors, the demand of I/O bandwidth is increasing. On the one hand, more and more lanes of high-speed interface are used, and on the other hand the transmission rate of interface is also raised gradually. The Network-on-Chip (NoC) of high-performance processors must be able to match the bandwidth requirements of various high-speed I/O interface, and must ensure that direct memory access (DMA) requests can be completed correctly. However, there are great differences in communication mechanism between various high-speed interface protocols and interconnection network protocols, which may lead to deadlock and other problems. This paper first analyzes NoC and high performance I/O, and proposes a method of designing high bandwidth I/O interface and a solution of resolving deadlock. NoC with deadlock resolution technique makes the I/O system more robust, and various limitations of NoC design can be reduced. Finally, based on a server processor, the proposed optimization method was implemented and evaluated. For 16-lane PCIe Gen4 interface, the read and write bandwidths reach up to 30GB/s respectively. In some special scenarios, deadlock is produced due to special transaction sequences, and the NoC can automatically detect the deadlock and release the deadlock.

Key words: network-on-chip, protocol conversion, high bandwidth, deadlock detection, deadlock resolution