Abstract: Aiming at the mid-bond test of hard-die based multi-tower 3D SoCs, this paper proposes a novel test time optimization algorithm considering the test resource constraints such as test access mechanism, Through-Silicon-Via count, and test power consumption. Once any remaining test resources do not satisfy the requirements of the die to be scheduled for testing, the test resources for the die that ends testing the earliest are released, until the die to be scheduled can be tested ahead of time as much as possible, thus obtaining partially pipelined testing between the newly scheduled die and the unfinished die. Five typical circuits in the ITC02 test benchmark circuit were selected, and two types of multi-tower 3D SoCs containing sub-towers were manually constructed. The results show that, compared with the existing algorithms, the proposed algorithm reduces the idle time blocks and significantly shortens the total test time. In addition, compared with increasing the number of TSVs, increasing the number of test pins can effectively reduce the total test time of a multi-tower 3D SoC. 

Key words: multi-tower 3D SoC, partially pipelined, test time, idle test time block