Abstract: Instruction-level parallelism obtained by the out-of-order superscalar processors is more and more limited. In order to obtain higher instruction-level parallelism, more out-of-order execution and control resources must be added. As the processor architecture changes, the value prediction technology can achieve higher data parallelism with less hardware overhead based on the existing mainstream processor micro-architecture, and further improve the processor's out-of-order execution performance. This paper proposes a context value predictor (RH-VTAGE) based on real historical feedback, which controls the prediction accuracy of RH-VTAGE by setting a failure list and a prediction accuracy table, and reduces the pipeline recovery overhead when the prediction fails. Meanwhile, at the final stage of the value predictor, a real historical feedback control counter is added, and an adaptive confidence control logic is designed to dynamically adjust the confidence according to the probability for different types of instructions. The actual test results show that, compared with other predictors, RH-VTAGE's integer prediction performance has no obvious effect, but the performance of floating-point programs is improved by 31.2% at most.

Key words: value predict, processor, predict table