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ZHANG Yu er, XI Yuhao, LIU Peng.
Designing and optimizing RISC-V instruction set functionality based on multi-operand acceleration
[J]. Computer Engineering & Science, 2025, 47(6): 968-975.
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MING Tianbo1, LIU Biwei1, 2, HU Chunmei1, 2, WU Zhenyu1, 2, SONG Ruiqiang1, 2, SONG Fangfang1.
An automated physical compiler for multi-port register files
[J]. Computer Engineering & Science, 2025, 47(6): 976-987.
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XIE Yang, LI Chen, CHEN Xiaowen.
A near-data processing architecture for data-intensive applications
[J]. Computer Engineering & Science, 2025, 47(5): 797-810.
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LIAN Zihan, HE Weifeng.
High-performance processor design based on dynamic timing slack exploitation
[J]. Computer Engineering & Science, 2025, 47(2): 219-227.
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WANG Qiang, SUN Yan-jie, QI Xing-yun, XU Jia-qing.
Bowtie 2-NUMA: Gene sequence alignment application with NUMA architecture adaptability
[J]. Computer Engineering & Science, 2024, 46(12): 2117-2127.
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ZHU Wen-long, JIANG Jia-zhi, HUANG Dan, XIAO Nong.
ParM: A heterogeneous programming model for domestic processors
[J]. Computer Engineering & Science, 2023, 45(9): 1521-1531.
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ZHOU Li, ZHAO Zhi-qiao, PAN Guo-teng, TIE Jun-bo, ZHAO Wang.
RISC-V based design of graph convolutional neural network accelerator
[J]. Computer Engineering & Science, 2023, 45(12): 2113-2120.
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LU Song, JIANG Ju-ping, REN Hui-feng.
Quick customization for RISC-V processor based on FPGA
[J]. Computer Engineering & Science, 2022, 44(10): 1747-1752.
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MU Ming-ren, JIA Hai-peng, ZHANG Yun-quan, DENG Ming-sen, QU Guo-yuan, WEI Da-zhou, ZHANG Guang-ting.
Optimization of median filtering algorithm based on ARM architecture
[J]. Computer Engineering & Science, 2022, 44(10): 1738-1746.
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DENG Ping, ZHU Xiao-long, SUN Hai-yan, Ren Yi.
Design and implementation of RISC-V assembler supporting vector instructions
[J]. Computer Engineering & Science, 2020, 42(12): 2179-2185.
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WANG Yao-hua, GUO Yang.
The review of state-of-the-art processor architectures for high performance computing
[J]. Computer Engineering & Science, 2020, 42(10高性能专刊): 1742-1748.
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TANG Zhiqiang,ZHU Zicong.
Reform and innovation of digital logic curriculum
for computer science majors
[J]. J4, 2014, 36(A2): 159-161.
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XU Chuanfu1,WANG Rong2,CHE Yonggang1,WANG Zhenghua1.
Evaluation of the Trace Effects in LargeScale Parallel Performance Simulation and Discussion of Some Resolutions
[J]. J4, 2012, 34(3): 67-73.
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TANG Tao,YANG Xuejun.
A Survey of the Programming Methods for Heterogeneous Systems
[J]. J4, 2012, 34(3): 29-34.
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CHEN Wei,WANG Zhiying,CHEN Xuhao,SHEN Li,LU Hongyi,XIAO Nong.
A DICacheBased Hybrid Threaded Interpretation Technique
[J]. J4, 2012, 34(2): 50-55.
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