[1] |
JIANG Jing-fei, HE Yuan-hong, XU Jin-wei, XU Shi-yao, QIAN Xi-fu.
NM-SpMM:A semi-structured sparse matrix multiplication algorithm for domestic heterogeneous vector processors
[J]. Computer Engineering & Science, 2024, 46(07): 1141-1150.
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[2] |
SHI Yu, DONG Pan, ZHANG Li-jun.
An irregular sparse matrix SpMV method
[J]. Computer Engineering & Science, 2024, 46(07): 1175-1184.
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[3] |
WANG Jie, FU Dan-yang, .
ROB compression method based on RISC-V superscalar processor
[J]. Computer Engineering & Science, 2024, 46(07): 1185-1192.
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[4] |
WEI Yi, YANG Zhi-jie, TIE Jun-bo, SHI Wei, ZHOU Li, WANG Yao, WANG Lei, XU Wei-xia.
A multistage dynamic branch predictor based on Hummingbird E203
[J]. Computer Engineering & Science, 2024, 46(05): 785-793.
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[5] |
WANG Yu-hua, HE Jun-fei, ZHANG Yu-qi, XU Yue-zhu, CUI Huan-yu.
DRM: A GPU-parallel SpMV storage format based on iterative merge strategy
[J]. Computer Engineering & Science, 2024, 46(03): 381-394.
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[6] |
ZHOU Li, ZHAO Zhi-qiao, PAN Guo-teng, TIE Jun-bo, ZHAO Wang.
RISC-V based design of graph convolutional neural network accelerator
[J]. Computer Engineering & Science, 2023, 45(12): 2113-2120.
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[7] |
WANG Xin, PENG Jian.
Implementation and optimization of HYB-based SpMV on the new-generation Sunway architecture
[J]. Computer Engineering & Science, 2023, 45(10): 1754-1762.
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[8] |
LI Fei, GUO Shao-zhong, ZHOU Bei, SONG Guang-hui, HAO Jiang-wei, XU Jin-chen.
Performance optimization of RISC-V basic math library
[J]. Computer Engineering & Science, 2023, 45(09): 1532-1543.
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[9] |
SUN Cai-xia, SUI Bing-cai, DENG Quan, ZHENG Zhong, NI Xiao-qiang, WANG Yong-wen.
A hybrid ISA processor compatible with RISC-V at application level
[J]. Computer Engineering & Science, 2023, 45(08): 1347-1353.
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[10] |
LI Xiao-ling, FANG Jian-bin, MA Jun, TAN Shuang, TAN Yu-song.
Automated task allocation of sparse matrix computation based on supervised learning
[J]. Computer Engineering & Science, 2023, 45(05): 782-789.
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[11] |
LU Song, JIANG Ju-ping, REN Hui-feng.
Quick customization for RISC-V processor based on FPGA
[J]. Computer Engineering & Science, 2022, 44(10): 1747-1752.
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[12] |
NIU Shi-quan.
Lightweight secure memory: Security enhancement for RISC-V embedded microprocessors
[J]. Computer Engineering & Science, 2021, 43(08): 1360-1365.
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[13] |
XU Zi-chen, CUI Ao, WANG Yu-hao, LIU Tao.
A containerization method for reinforcement learning based on RISC-V architecture
[J]. Computer Engineering & Science, 2021, 43(02): 266-273.
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[14] |
DENG Ping, ZHU Xiao-long, SUN Hai-yan, Ren Yi.
Design and implementation of RISC-V assembler supporting vector instructions
[J]. Computer Engineering & Science, 2020, 42(12): 2179-2185.
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[15] |
TAN Zhaonian,JI Weixing,AKREM Benatia,GAO Jianhua,LI Anmin,WANG Yizhuo.
An SpMV partitioning and optimization algorithm
on heterogeneous computing platforms
[J]. Computer Engineering & Science, 2019, 41(04): 590-597.
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